Coreless ETS (Embedded Trace Substrate) BT IC substrate eliminates the thick glass-cloth reinforced core to achieve ultra-thin profiles (as thin as 0.13 mm for 2-6 layer structures) and superior warpage control. By embedding the outermost circuit pattern directly into the BT insulating material, ETS ...
Coreless ETS (Embedded Trace Substrate) BT IC substrate eliminates the thick glass-cloth reinforced core to achieve ultra-thin profiles (as thin as 0.13 mm for 2-6 layer structures) and superior warpage control. By embedding the outermost circuit pattern directly into the BT insulating material, ETS technology enables fine line/space down to 12/12 μm (sample) and 12/18 μm (mSAP production). The coreless construction reduces overall package height for FC-CSP applications (3*3 mm to 19*19 mm) with bump pitches ≥0.15 mm. Available in 2-8 layer configurations, these substrates are ideal for ultra-thin mobile devices, wearable electronics, and high-density SiP modules where thickness and warpage are critical constraints.
Coreless construction (as thin as 0.13 mm) enables thinner smartphones, tablets, and wearables without sacrificing interconnect density.
The ultra-thin profile and reduced warpage make ETS BT substrates ideal for smartwatches, hearables, and health monitoring devices.
Coreless technology supports multi-chip integration in compact form factors, essential for RF front-end modules and sensor hubs.
Fine line/space (12/18 μm) and bump pitch ≥0.15 mm enable high I/O count in compact package sizes (3*3 mm to 19*19 mm).
The coreless structure significantly reduces package warpage compared to conventional substrates, critical for large-die flip-chip assemblies and assembly yield optimization.
english
Deutsch
Русский
Español
العربية
